System-on-chip (SoC) technology is integrating multiple functional blocks on a single silicon chip. The multiple functional blocks may include digital circuits, analog circuits, mixed-signal circuits or any combination thereof. This technology reduces the development cycle and manufacturing costs while increasing product reliability, functionality and performance.
As semiconductor devices advance to submicron sizes, integrated circuit design margins have become very small. Therefore, a proper estimate of aging-induced defects will help designers optimize design margins so as to achieve a balance between reliability and cost. Simulation tools such as Simulation Program with Integrated Circuits Emphasis (SPICE) can be used to simulate aging-induced defects. However, it is not widely known how degradation mechanisms propagate in a SoC chip as a function of a variety of operating conditions. Thus, an aging model is needed to predict semiconductor degradation.